Electronics devices contain many interfaces which transfer data serially. Some examples are USB, Ethernet, Firewire and Rambus. These interfaces have high bit rates which must be captured reliably at the receiver. Most receivers generate a clock at the serial bit rate to sample the serial data before decoding. To do this they typically use a phase-locked loop (PLL) circuit to find the clock signal within the received serial data. Then, they clock the received serial data into a shift register using a synchronized clock which is at the serial bit rate but offset in phase from the serial data transitions so as to sample the serial data when it is stable. Sampled serial data above a preselected threshold value is a one and sampled serial data that is below that threshold value is a zero.
This method works well at low bit frequencies, such as less than 100 MHz, since accumulated timing errors will still generate a clock edge near the correct time. At frequencies higher than 100 MHz, variation in the timing of the serial sampling clock, from process, temperature or voltage changes, can cause incorrect sampling of the data.